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X9455
Data Sheet November 10, 2004 FN8202.0
Dual Two-wiper Digitally-Controlled (XDCPTM) Potentiometer
The X9455 integrates 2 digitally controlled potentiometers (XDCP), each one with dual wipers, on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to wiper terminals through switches. The position of each wiper on the array is controlled by the user through the U/D or 2-wire bus interface. Each potentiometer wiper has associated with it two volatile Wiper Counter Register (WCR) and each WCR has associated with it four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. The contents of the default data registers (DR0A0, DR0B0, DR1A0, DR1B0) are loaded into the WCR on power up. The DCP can be used as a four-terminal potentiometer in a wide variety of applications including the programming of bias voltages, window comparators, and three resistor programmable networks.
Features
* Dual Two-wiper solid state potentiometer * 256 Resistor tap points-0.4% resolution * 2-wire serial interface for Write, Read, and transfer operations of the potentiometer * Up/Down interface for individual potentiometer wipers * Wiper resistance, 40 typical * Non-volatile storage of wiper positions * Power On Recall Loads saved wiper position on Power Up. * Standby Current < 20A Max * Maximum Wiper Current: 3mA * VCC: 2.7V to 5.5V operation * 2.8k,10k, 50k, 100k version of total pot resistance * Endurance: 100,000 Data changes per bit per register * 100 yr. data retention * 24-Lead TSSOP
Ordering Information
PART NUMBER X9455YV24-2.7 X9455YV24I-2.7 X9455WV24-2.7 X9455WV24I-2.7 X9455UV24-2.7 X9455UV24I-2.7 X9455TV24-2.7 X9455TV24I-2.7 RTOTAL 2.8k 2.8k 10k 10k 50k 50k 100k 100k PACKAGE 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP 24-lead TSSOP OPERATING TEMP RANGE (C) 0 to 70 -40 to +85 0 to 70 -40 to +85 0 to 70 -40 to +85 0 to 70 -40 to +85
Pinout
X9455 (24-LD TSSOP) TOP VIEW
DS0 A0 RW0B NC NC U/D Vcc RL0 RH0 RW0A A2 WP 1 2 3 4 5 6 7 8 9 10 11 12 X9455 18 17 16 15 14 13 Vss RW1B NC NC A1 SDA 24 23 22 21 20 19 DS1 SCL RL1 RH1 RW1A CS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9455 Functional Diagram
VCC A2 A1 A0 SDA SCL Up/Down Interface POWERUP, INTERFACE CONTROL AND STATUS 2-wire Interface WCR0A DR0A0 DR0A1 DR0A2 DR0A3 WCR0B DR0B0 DR0B1 DR0B2 DR0B3
RH0
RH1
DCP0
WCR1A DR1A0 DR1A1 DR1A2 DR1A3
WCR1B DR1B0 DR1B1 DR1B2 DR1B3
DCP1
DS0 DS1 CS U/D
VSS
WP
RW0A RW0B RL0
RW1A RW1B
RL1
Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SYMBOL DS0 A0 RW0B NC NC U/D VCC RL0 RH0 RW0A A2 WP SDA A1 NC NC RW1B VSS CS RW1A RH1 RL1 SCL DS1 BRIEF DESCRIPTION Wiper Selection input for Up/Down interface Device Address for 2-wire interface Second Wiper Terminal of DCP0 No Connect No Connect Increment/Decrement for Up/Down interface System Supply Voltage Low Terminal of DCP0 High Terminal of DCP0 First Wiper Terminal of the DCP0 Device Address for 2-wire interface Hardware Write Protect (Active low) Serial Data Input/Output for 2-wire interface Device Address for 2-wire interface No Connect No Connect Second Wiper Terminal of DCP1 System Ground Chip select for Up/Down interface First Wiper Terminal of DCP1 High Terminal of DCP1 Low Terminal of DCP1 Serial Clock for 2-wire interface Wiper selection input for Up/Down interface
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Absolute Maximum Ratings
Junction Temperature under bias. . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any digital interface pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage at any DCP pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to VCC Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Recommended Operating Conditions
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) (Note 4) Limits . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS Y, W, U, T versions respectively -20 25C, each DCP 0.75 See test circuit Wiper current = VCC -3.0 50 MIN TYP (Note 4) 2.8, 10, 50, 100 +20 50 2.0 +3.0 150 MAX UNIT k % mW % mA
PARAMETER End to end resistance End to end resistance tolerance Power rating
RTOTAL Matching IW (Note 5) RW
DCP to DCP resistance matching Wiper current Wiper resistance
RTOTAL Vss Vcc -120 0.4 V dBV % +1 +0.3 300 -20 +20 10/10/25 0.1 10 MI (Note 3) MI (Note 3) ppm/C ppm/C pF A
VTERM
Voltage on any DCP pin Noise (Note 5) Resolution Absolute linearity (Note 1) Relative linearity (Note 2) Temperature coefficient of resistance (Note 5) Ratiometric Temperature (Note 5) Coefficient V(RH0)=V(RH1)=VCC V(RL0)=V(RL1)=VSS Ref: 1kHz
-1 -0.3
CH/CL/CW IOL
Potentiometer Capacitance (Note 5) Leakage on DCP pins
See equivalent circuit Voltage at pin from VSS to VCC
DC Electrical Specifications
SYMBOL ICC1 ICC2 ICC3 ISB IL
Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) fSCL = 200kHz; (for U/D interface, increment, decrement) fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) Voltage at pin from VSS to VCC -10 MIN MAX 3 3 5 20 10 UNITS mA mA mA A A
PARAMETER VCC supply current (Volatile write/read) VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Leakage current, bus interface pins
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DC Electrical Specifications
SYMBOL VIH VIL VOL Input HIGH voltage Input LOW voltage SDA pin output LOW voltage IOL = 3mA Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS MIN VCC x 0.7 -1 MAX VCC + 1 VCC x 0.3 0.4 UNITS V V V
PARAMETER
Endurance and Data Retention
PARAMETER Minimum endurance Data retention MIN 100,000 100 UNITS Data changes per bit Years
Capacitance
SYMBOL TEST TEST CONDITIONS VOUT = 0V VIN = 0V MAX 8 6 UNITS pF pF CIN/OUT (Note 5) Input / Output capacitance (SDA) CIN (Note 5)
and A0)
Input capacitance (DS0, DS1, CS, U/D, SCL, WP, A2, A1
Power-Up Timing
SYMBOL tD (Notes 5, 9) PARAMETER Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall completed, and communication interfaces ready for operation. MAX 2 UNITS ms
A.C. Test Conditions
Input Pulse Levels Input rise and fall times Input and output timing threshold level External load at pin SDA VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 2.3k to VCC and 100 pF to VSS
2-Wire Interface Timing (s)
SYMBOL fSCL tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR (Note 5) tF (Note 5) tAA (Note 5) tDH tIN (Note 5) tBUF (Note 5) Clock Frequency Clock High Time Clock Low Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Pulse Width Suppression Time at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) 1200 0 50 600 1300 600 600 600 100 30 300 300 0.9 PARAMETER MIN MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns s ns ns ns
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2-Wire Interface Timing (s) (Continued)
SYMBOL tSU:WPA (Note 5) tHD:WPA (Note 5) A0, A1, A2 and WP Setup Time A0, A1, A2 and WP Hold Time PARAMETER MIN 600 600 MAX UNITS ns ns
SDA vs. SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA SDA (Input Timing)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (Output Timing)
tDH
tBUF
WP, A0, A1, and A2 Pin Timing
START SCL STOP
Clk 1
SDA IN tSU:WP WP, A0, A1, or A2 tHD:WP
Increment/Decrement Timing
SYMBOL tCI tID (Note 5) tDI (Note 5) tIL tIH tIC tCPHS tCPHNS (Note 5) tIW (Note 5) tCYC tR, tF (Note 5) CS to SCL Setup SCL HIGH to U/D, DS0 or DS1 change U/D, DS0 or DS1 to SCL setup SCL LOW period SCL HIGH period SCL inactive to CS inactive (Nonvolatile Store Setup Time) CS deselect time (STORE) CS deselect time (NO STORE) SCL to RW change SCL cycle time SCL input rise and fall time 5 500 PARAMETER MIN 600 600 600 2.5 2.5 1 10 1 100 500 TYP (Note 4) MAX UNITS ns ns ns s s s ms s s s s
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Increment/Decrement Timing
CS tCYC tCI SCL tIL tIH tIC tCPHS 90% 90% 10% tID tDI tF tR tCPHNS
U/D
DS0, DS1 tIW RW MI (3)
High-Voltage Write Cycle Timing
SYMBOL tWC (Notes 5, 8) Non-volatile write cycle time PARAMETER TYP 5 MAX 10 UNITS ms
XDCP Timing
SYMBOL PARAMETER MIN 5 MAX 20 UNITS s tWRL (Note 5) SCL rising edge to wiper code changed, wiper response time after instruction issued (all load instructions) NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/255 + V(RL), with n from 0 to 255. 2. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) + MI)]/MI, with n from 0 to 254 3. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/255. 4. Typical values are for TA = 25C and nominal supply voltage. 5. This parameter is not 100% tested. 6. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2)] x 106, with T1 & T2 being 2 temperatures, and n from 0 to 255. 7. Measured with wiper at tap position 255, RL grounded, using test circuit. 8. tWC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a valid "Store" operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle. 9. The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power up, the data sheet parameters for the DCP do not fully apply until tD after VCC reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant store, bring the CS pin high before or concurrently with the VCC pin on power up.
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Test Circuit
Test Point
DCP Select (DS1-DS0) The DS1-DS0 select one of the four DCPs for an Up/Down interface operation. Hardware Write Protect Input (WP)
RW Force Current
When the WP pin is set low, "write" operations to non volatile DCP Data Registers are disabled. This includes both 2-wire interface non-volatile "Write", and Up/Down interface "Store" operations.
Equivalent Circuit
RTOTAL RH CH CW CL RL
DCP Pins
RH0, RL0, RH1, RL1 These pins are equivalent to the terminal connections on mechanical potentiometers. Since there are two DCPs, there is one set of RH and RL for each DCP. RW0A, RW0B, RW1A, and RW1B
RW
The wiper pins are equivalent to the wiper terminals of mechanical potentiometers. Since there are two wipers per DCP, there are four RW pins.
Pin Descriptions
Bus Interface Pins
Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for the 2-wire interface. It receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. SDA requires an external pull-up resistor, since it's an open drain output. Serial Clock (SCL) This input is the serial clock of the 2-wire and Up/Down interface. Device Address (A2-A0) The Address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the X9455. A maximum of 8 devices may occupy the 2-wire serial bus. Chip Select (CS) When the CS pin is low, increment or decrement operations are possible using the SCL and U/D pins. The 2-wire interface is disabled at this time. When CS is high, the 2-wire interface is enabled. Up or Down Control (U/D) The U/D input pin is held HIGH during increment operations and held LOW during decrement operations.
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X9455 Principles of Operation
The X9455 is an integrated circuit incorporating two resistor arrays with dual wipers on each array, their associated registers and counters, and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: * Resistor Array * Up/Down Interface * 2-wire Interface switches, one connected to each of the wiper pins (RWiA and RWiB). Within each individual array only one switch of each wiper may be turned on at a time. These switches are controlled by two Wiper Counter Register (WCR). The 8-bits of the WCR are decoded to select and enable one of 256 switches. Note that each wiper has a dedicated WCR. When all bits of a WCR are zeroes, the switch closest to the corresponding RL pin is selected. When all bits of a WCR are ones, the switch closest to the corresponding RH pin is selected. The WCRs are volatile and may be written directly. There are four non-volatile Data Registers (DR) associated with each WCR. Each DR can be loaded into WCR. All DRs and WCRs can be read or written.
Resistor Array Description
The X9455 is comprised of two resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi inputs). (See Figure 1.) Each array has two independent wipers. At both ends of each array and between each resistor segment are two
Power Up and Down Requirements
During power up CS must be high to avoid inadvertant "store" operations. At power up, the contents of Data Registers Level 0 (DR0A0, DR0B0, DR1A0, and DR1B0), are loaded into the corresponding wiper counter register.
"i" is either 0 or 1 RHi Four Non-Volatile Data Registers DRiA0, DRiA1, DRiA2, and DRiA3 WCRiA[7:0] 255 = FF hex Volatile 8-bit Wiper Counter Register WCRiA One of 256 Decoder 254 . . . 1 0
WCRiA[7:0] = 00 hex
2-wire and Up/Down Interfaces
WCRiB[7:0] 255 = FF hex 254 Four Non-Volatile Data Registers DRiB0, DRiB1, DRiB2, and DRiB3 Volatile 8-bit Wiper Counter Register WCRiB WCRiB[7:0] = 00 hex . . . 1 0 RWiA RLi RWiB
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
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X9455 Up/Down Interface Operation
The SCL, U/D, CS, DS0 and DS1 inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and SCL inputs. HIGH to LOW transitions on SCL will increment or decrement (depending on the state of the U/D input) a wiper counter register selected by DS0 and DS1. The output of this counter is decoded to select one of 256 wiper positions along the resistor array. The value of the counter is stored in nonvolatile data register Level 0 of the corresponding WCR whenever CS transitions HIGH while the SCL and WP inputs are HIGH (See Table 1). During a "Store" operation bits WCRSel1 and WCRSel0 in the status register must be both "0", which is their power up default value. Other combinations are reserved and must not be used. The system may select the X9455, move a wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep SCL LOW while taking CS HIGH. The new wiper position is maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. The 2-wire interface is disabled while CS remains LOW.
TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL DS1 0 1 1 0 DS0 0 1 0 1 SELECTED WIPER CONTROL REGISTER Wiper A of DCP0 Wiper B of DCP0 Wiper A of DCP1 Wiper B of DCP1 TABLE 2. MODE SELECTION FOR UP/DOWN CONTROL CS L L H SCL U/D H L X Wiper Up Wiper Down Store Wiper Position to nonvolatile memory if WP pin is high. No store, return to standby, if WP pin is low. Standby* No Store, Return to Standby Wiper Up (not recommended) Wiper Down (not recommended) MODE
H
X L L L
X X H L
*While in Standby, the 2-wire interface is enabled
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SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
2-Wire serial interface
Protocol Overview
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X9455 operates as a slave in all applications. All 2-wire interface operations must begin with a START, followed by a Slave Address byte. The Slave Address selects the X9455, and specifies if a Read or Write operation is to be performed. All Communication over the 2-wire interface is conducted by sending the MSB of each byte of data first.
Serial Stop Condition
All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus (See Figure 2).
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 3). The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 0101, and the Device Address bits matching the logic state of pins A2, A1, and A0 (See Figure 4). If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state.
Serial Clock and Data
Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions (See Figure 2). On power up of the X9455, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met (See Figure 2).
SCL from Master 1
8
9
SDA Output from Transmitter
SDA Output from Receiver START ACK
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
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Slave Address Byte
Following a START condition, the master must output a Slave Address Byte (Refer to figure 4.). This byte includes three parts: * The four MSBs (SA7-SA4) are the Device Type Identifier, which must always be set to 0101 in order to select the X9455. * The next three bits (SA3-SA1) are the Device Address bits (AS2-AS0). To access any part of the X9455's memory, the value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. * The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. When the R/W bit is "1", then a Read operation is selected. A "0" selects a Write operation.
SA7 0 SA6 1 SA5 0 SA4 1 SA3 AS2 SA2 AS1 Byte load completed by issuing STOP. Enter ACK Polling
Issue START
Issue Slave Address Byte (Read or Write)
Issue STOP
ACK returned?
NO
YES SA1 AS0 SA0 High Voltage R/W complete. Continue command sequence. Device Type Identifier Device Address Read or Write NO
YES Continue normal Read or Write command sequence
Issue STOP
SLAVE ADDRESS BIT(S) SA7-SA4 SA3-SA1 SA0
DESCRIPTION Device Type Identifier Device Address Read or Write Operation Select FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE
PROCEED
FIGURE 4. SLAVE ADDRESS (SA) FORMAT
2-Wire Serial Interface Operation
X9455 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are 2 Digital Potentiometers, referred to as DCP0, and DCP1. Each potentiometer has two volatile Wiper Control Registers (WCRs). Each wiper has four non-volatile registers to store wiper position or general data. See Table 2 for register numbering.
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X9455 initiates an internal high voltage write cycle. This cycle typically requires 5 ms. During this time, any Read or Write command is ignored by the X9455. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed. During acknowledge polling, the master first issues a START condition followed by a Slave Address Byte. The Slave Address Byte contains the X9455's Device Type Identifier and Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is busy within the high voltage cycle, then no ACK is returned. If the high voltage cycle is completed, an ACK is returned and the master can then proceed with a new Read or Write operation. (Refer to figure 5.)
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TABLE 3. REGISTER NUMBERING STATUS REG (NOTE 1) (Addr: 07H) Reserved bits 7-3 Reserved DRSel1 bit 2 X 0 0 1 1 DRSel0 bit 1 X 0 1 0 1 NVEnable bit 0 0 1 1 1 1 REGISTERED SELECTED (NOTE 2) DCP0 (Addr: 00h) WCR0A DR0A0 DR0A1 DR0A2 DR0A3 (Addr: 11h) WCR0B DR0B0 DR0B1 DR0B2 DR0B3 DCP2 (Addr: 02h) WCR1A DR1A0 DR1A1 DR1A2 DR1A3 (Addr: 01h) WCR1B DR1B0 DR1B1 DR1B2 DR1B3
NOTES:To read or write the contents of a single Data Register or Wiper Register: 1. Load the status register (using a write command) to select the row. (See Figure 6.) Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This Status Register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example, writing `03h' to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to move to WCR3. Writing a 0 to bit `0' of the Status Register specifies that the subsequent read or write command will access a Wiper Counter Register. Each WCR can be written to individually, without affecting the contents of any other. 2. Access the desired DR or WCR using a new write or read command (see Figure 7 for write and Figure 9 for read.) Specify the desired column (DCP number) by sending the DCP address as part of this read or write command.
The registers are organized in pages of four, with one page consisting of the four volatile WCRs, a second page consisting of the Level 0 Data Registers, and so forth. These pages can be written four bytes at time. In this manner all four potentiometer WCRs can be updated in a single serial write (see Page Write Operation), as well as all four registers of a given page in the DR array. The unique feature of the X9455 device is that writing or reading to a Data Register of a given wiper automatically updates the WCR of that wiper with the new value. In this manner data can be moved from a particular wiper register to that wiper's WCR just by performing a 2-wire read operation. Simultaneously, that data byte can be utilized by the host.
volatile wiper registers if "1". Table 3 shows this register organization.
Wiper Addressing for 2-wire Interface
Once the Data Register Level has been selected by a 2-wire instruction, then the wiper is determined by the Address Byte of the following instruction. Note again that this enables a complete page write of all four potentiometers at once a particular Wiper Register has been chosen. The register addresses accessible in the X9455 include:
Status Register Organization
The Status Register (SR) is used in read and write operations to select the appropriate wiper register. Before any wiper register can be accessed, the SR must be set to the correct value. It is accessed by setting the Address Byte to 07h. See Table 3. Do this by writing the slave address followed by a byte address of 07h. The SR is volatile and defaults to 00h on power up. It is an 8-bit register containing three control bits in the 3 LSBs as follows:
7 6 5 4 3 2 WCRSel1 1 WCRSel0 0 NVEnable
Reserved
Bits WCRSel1 and WCRSel0 determine which Data Register of a wiper is selected for a given operation. NVEnable is used to select the volatile WCR if "0", and one of the non
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If bit 0 of data byte = 1, DR contents move to WCR during this ACK period S t a r t
Signals from the Master
Slave Address
Status Register Address
DR select Data
S t o p
Signal at SDA 0101 Signals from the Slave
0 A C K
00000111 A C K
00000x x1 A C K
FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER)
TABLE 4. ADDRESSING FOR 2-WIRE INTERFACE ADDRESS BYTE ADDRESS (HEX) 0 1 2 3 4 5 6 7 CONTENTS Wiper 0A Wiper 1B Wiper 1A Wiper 0B Not Used Not Used Not Used Status Register
For example, to write 3Ahex to the Level 1 Data Register of wiper 1A (DR1A1) the following sequence is required: START Slave Address ACK Address Byte ACK Data Byte ACK
respective DR.)
0101 0000 0000 0111 0000 0011
(Hardware Address = 000, and a Write command) (Indicates Status Register address) (Data Register Level 1 and NVEnable selected)
(note: at this ACK, the WCRs are all updated with their
STOP START Slave Address ACK Address Byte ACK Data Byte ACK STOP 0101 0000 0000 0010
(Write Data Byte 3Ah) (Hardware address = 000, Write command) (Access Wiper 1A)
All other address bits in the address byte must be set to "0" during 2-wire write operations and their value should be ignored when read.
0011 1010
Byte Write Operation
For any Byte Write operation, the X9455 requires the Slave Address byte, an Address Byte, and a Data Byte (See Figure 7). After each of them, the X9455 responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if the write operation is to a volatile register (WCR, or SR), the X9455 is ready for the next read or write operation. If the write operation is to a nonvolatile register (DR), and the WP pin is high, the X9455 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X9455 does not respond to any requests from the master. The SDA output is at high impedance. The SR bits and WP pin determine the register being accessed through the 2-wire interface. See Table 2 on page 9. As noted before, any write operation to a Data Register (DR), also transfers the contents of all the data registers in that row to their corresponding WCR.
During the sequence of this example, WP pin must be high, and A0, A1, and A2 pins must be low. When completed, the DR1A1 register and the WCR1A of Wiper 1A will be set to 3Ah, and the other data registers in Row 1 will transfer their contents to the respective WCRs.
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X9455
Write Signals from the Master S t a r t Slave Address Address Byte Data Byte S t o p
Signal at SDA Signals from the Slave
01 01
0
A C K A C K A C K
FIGURE 7. BYTE WRITE SEQUENCE
Page Write Operation
As stated previously, the memory is organized as a single Status Register (SR), and four pages of four registers each. Each page contains one Data Register for each wiper. Normally a page write operation will be used to efficiently update all four Data Registers and WCR in a single Write command. Note the special sequence for writing to a page: First wiper 0A, then 1B, then 1A, then 0B as shown in Figure 9.
WCR DR Level 0 DR Level 1 DR Level 2 DR Level 3 WCR0A WCR1B WCR1A WCR0B DR0A0 DR0A1 DR0A2 DR0A3 DR1B0 DR1B1 DR1B2 DR1B3 DR1A0 DR1A1 DR1A2 DR1A3 DR0B0 DR0B1 DR0B2 DR0B3
transmit up to 4 bytes (See Figure 9). After the receipt of each byte, the X9455 responds with an ACK, and the internal WCR address is incremented by one. The page address remains constant. When the address reaches the end of the page, it "rolls over" and goes back to the first byte of the same page. For example, if the master writes three bytes to a page starting at location DR1A2, the first two bytes are written to locations DR1A2 and DR0B2, while the last byte is written to location DR0A2. Afterwards, the WCR address would point to location DR1B2. If the master supplies more than four bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the loading of Data Bytes by issuing a STOP condition, which initiates the nonvolatile write cycle. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. If the WP pin is low, the nonvolatile write cycle doesn't start and the bytes are discarded. Notice that the Data Bytes are also written to the WCR of the corresponding WCRs, therefore in the above example, WCR1A, WCR0B, and WCR0A are also written, and WCR1B is updated with the contents of DR1B2.
FIGURE 8. PAGE WRITE SEQUENCE* *Page writes may wrap around to the first address on a page from the last address.
In order to perform a Page Write operation to the memory array, the NVEnable bit in the SR must first be set to "1". A Page Write operation is initiated in the same manner as the Byte Write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can
Write Signals from the Master S t a r t
2Slave Address
Data Byte (1)
Data Byte (n)
Signal at SDA
01 01
Signals from the Slave
0
A C K A C K A C K A C K
FIGURE 9. PAGE WRITE OPERATION
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X9455
Move/Read Operation
The Move/Read operation simultaneously reads the contents of a data register and moves the contents into the corresponding DCP's WCR and all wipers will have their WCR's updated with the data register values from the row that was read. Move/Read operation consists of a one byte, or three byte instruction followed by one or more Data Bytes (See Figure 10). To read an arbitrary byte, the master initiates the operation issuing the following sequence: a START, the Slave Address byte with the R/W bit set to "0", an Address Byte, a second START, and a second Slave Address byte with the R/W bit set to "1". After each of the three bytes, the X9455 responds with an ACK. Then the X9455 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the Move/Read operation (issuing a STOP condition) following the last bit of the last Data Byte. The first byte being read is determined by the current wiper address and by the Status Register bits, according to Table 1 on page 11. If more than one byte is read, the WCR address is incremented by one after each byte, in the same way as during a Page Write operation. After reaching WCR0B, the WCR address "rolls over" to WCR0A. On power up, the Address pointer is set to the Data Register 0 of WCR0A.
One or more Data Bytes Signals from the Master S t a r t Slave Address with R/W=0 S t a r t Slave Address with R/W=1 S t o p
Address Byte
A C K
A C K
Signal at SDA 01 01 Signals from the Slave 0 A C K A C K 01 01 1 A C K
First Read Data Byte
Last Read Data Byte
Setting the Current Address
Current Address Read
Random Address Read
FIGURE 10. MOVE/READ SEQUENCE
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X9455 Applications information
Basic Configurations of Electronic Potentiometers
VR RH POTi RW0 RW1 RW1A RW1B POT1 POT0 RW0A RW0B
RL
Four terminal Potentiometer; Variable voltage divider
Four-Wiper DCP
Application Circuits
V+ WINDOW COMPARATOR } VUL VS VO SHUNT LIMITER mR nR } + VS
+
pR }
V+ + VLL
VR
+ VO
FUNCTION GENERATOR C mR nR pR } } } + VO
+
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X9455
PROGRAMMABLE STATE VARIABLE FILTER C
PROGRAMMABLE LADDER NETWORKS mR nR } } pR } C1 R1
mR1 nR1 pR1 } } } VS + A2 + A1 C VO(HP) VO(BP)
mR2 nR2 pR2 + A3 R3 VO (LP) } } }
WIEN BRIDGE OSCILLATOR
GENERALIZED IMPEDANCE CONVERTER
ZIN = R4 R3 R2 R1 } } } } RW3 RW2 C1 + RW1 + C2 Z2 Z1 VO
Z1 Z2 *
(
R3 * R5 ) R4
R3 + R5
R4
Two Wiper DCP
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X9455
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.303 (7.70) .311 (7.90)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0-8 .020 (.50) .030 (.75) Detail A (20X) Seating Plane (1.78) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
(4.16) (7.72)
ALL MEASUREMENTS ARE TYPICAL
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN8202.0 November 10, 2004

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